october 2000 preliminary ? 2000 fairchild semiconductor corporation FDC602P rev b(w) FDC602P p-channel 2.5v powertrench ? ? ? ? specified mosfet general description this p-channel 2.5v specified mosfet uses a rugged gate version of fairchild?s advanced powertrench process. it has been optimized for power management applications with a wide range of gate drive voltage (2.5v ? 12v). applications ? battery management ? load switch ? battery protection features ? ?5.5 a, ?20 v r ds(on) = 0.035 ? @ v gs = ?4.5 v r ds(on) = 0.050 ? @ v gs = ?2.5 v ? fast switching speed ? high performance trench technology for extremely low r ds(on) d d d s d g supersot -6 tm 6 5 4 1 2 3 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain-source voltage ?20 v v gss gate-source voltage 12 v i d drain current ? continuous (note 1a) ?5.5 a ? pulsed ?20 maximum power dissipation (note 1a) 1.6 w p d (note 1b) 0.8 t j , t stg operating and storage junction temperature range ?55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r jc thermal resistance, junction-to-case (note 1) 30 c/w package marking and ordering information device marking device reel size tape width quantity .602 FDC602P 7?? 8mm 3000 units FDC602P
FDC602P rev b(w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain?source breakdown voltage v gs = 0 v, i d = ?250 a ?20 v ? bv dss === ? t j breakdown voltage temperature coefficient i d = ?250 a, referenced to 25 c ?14 mv/ c i dss zero gate voltage drain current v ds = ?16 v, v gs = 0 v ?1 a i gssf gate?body leakage, forward v gs = 12 v, v ds = 0 v 100 na i gssr gate?body leakage, reverse v gs = ?12 v, v ds = 0 v ?100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = ?250 a ?0.6 ?0.9 ?1.5 v ? v gs(th) === ? t j gate threshold voltage temperature coefficient i d = ?250 a, referenced to 25 c 3 mv/ c r ds(on) static drain?source on?resistance v gs = ?4.5 v, i d = ?5.5 a v gs = ?2.5 v, i d = ?4.5 a v gs = ?4.5 v, i d = ?5.5at j =125 c 0.027 0.038 0.038 0.035 0.050 0.053 ? i d(on) on?state drain current v gs = ?4.5 v, v ds = ?5 v ?20 a g fs forward transconductance v ds = ?5 v, i d = ?5.5 a 19 s dynamic characteristics c iss input capacitance 1456 pf c oss output capacitance 300 pf c rss reverse transfer capacitance v ds = ?10 v, v gs = 0 v, f = 1.0 mhz 150 pf switching characteristics (note 2) t d(on) turn?on delay time 15 27 ns t r turn?on rise time 11 20 ns t d(off) turn?off delay time 57 91 ns t f turn?off fall time v dd = ?10 v, i d = ?1 a, v gs = ?4.5 v, r gen = 6 ? 37 59 ns q g total gate charge 14 20 nc q gs gate?source charge 3 nc q gd gate?drain charge v ds = ?10 v, i d = ?5.5 a, v gs = ?4.5 v 5nc drain?source diode characteristics and maximum ratings i s maximum continuous drain?source diode forward current ?1.3 a v sd drain?source diode forward voltage v gs = 0 v, i s = ?1.3 a (note 2) ?0.7 ?1.2 v notes: 1. r ja is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mou nting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a. 78c/w when mounted on a 1in 2 pad of 2oz copper on fr-4 board. b. 156c/w when mounted on a minimum pad. 2. pulse test: pulse width = 300 s, duty cycle = 2.0% FDC602P
FDC602P rev b(w) typical characteristics 0 4 8 12 16 20 0 0.5 1 1.5 2 2.5 3 -v ds , drain to source voltage (v) -i d , drain current (a ) v gs =-4.5v -2.5v -3.0v -3.5v -2.0v 0.8 1 1.2 1.4 1.6 1.8 2 0 5 10 15 20 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -2.5v -3.5v -4.0v -4.5v -3.0v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistanc e i d = -5.5a v gs = -4.5v 0 0.02 0.04 0.06 0.08 0.1 0.12 1.522.533.544.55 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -3.0a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 4 8 12 16 20 0.5 1 1.5 2 2.5 3 -v gs , gate to source voltage (v) -i d , drain current (a ) t a = -55 o c 25 o c 125 o c v ds = -5.0v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -v sd , body diode forward voltage (v) -i s , reverse drain current (a ) v gs =-4.5v t a = 125 o c 25 o c -55 o c figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. FDC602P
FDC602P rev b(w) typical characteristics 0 1 2 3 4 5 0 3 6 9 12 15 18 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -5.5a v ds =-5.0v -10v -15v 0 400 800 1200 1600 2000 0 5 10 15 20 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage (v) -i d , drain current (a ) dc 10s 1s 100ms 100 ja = 156 o c/w t a = 25 o c 10ms 1ms 10 20 30 40 50 p(pk), peak transient power (w) single pulse r ja = 156c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) + r ja r ja = 156 o c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p (p k ) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1b. transient thermal response will change depending on the circuit board design. FDC602P
embossed carrier tape ssot-6 packaging configuration: fi g ur e 1.0 comp onent s lead er tape 500mm mi nimum or 125 emp t y poc kets traile r tap e 300mm mi nimum or 75 empt y poc kets ssot-6 tape leader and trailer configuration: fi g ur e 2.0 cover tape carrier tape note/comments packaging option ssot-6 packaging information stan da rd (no f l ow c ode ) d87z packaging type reel size tnr 7" di a tnr 13" qty per reel/tube/bag 3,000 10,000 box dimension (mm) 184x 187x 47 343x 343x 64 max qty per box 9,000 30,000 weight per unit (gm) 0.0158 0.0158 weight per reel (kg) 0.1440 0.4700 f63tnr label customize label antistatic cover tape 184mm x 187mm x 47mm pizza box fo r standar d option f63tnr label f63tnr label f63tnr label sampl e 343mm x 342mm x 64mm intermediate box fo r d87z option f63tnr label ssot-6 unit orientation 631 631 631 631 631 pin 1 lot: cbvk741b019 fsid: fdc633n d/c1: d9842 qty1: spec rev: spec: qty: 3000 d/c2: qty2: cpn: n/f: f (f63tnr)3 packaging description: ssot-6 parts are shipped in tape. the carrier tape is made from a dissipative (carbon filled) polycarbonate resin. the cover tape is a multilayer film (heat activated adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. these reeled parts in standard option are shipped with 3,000 units per 7" or 177cm diameter reel. the reels are dark blue in color and is made of polystyrene plastic (anti- static coated). other option comes in 10,000 units per 13" or 330cm diameter reel. this and some other options are described in the packaging information table. these full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a fairchild logo printing. one pizza box contains three reels maximum. and these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. supersot tm -6 tape and reel data august 1999, rev. c ?2000 fairchild semiconductor international
? 1998 fairchild semiconductor corporation p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 8mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 8mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed ssot-6 embossed carrier tape configuration: fi g ure 3.0 ssot-6 reel configuration: fi g ure 4.0 dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc ssot-6 (8mm) 3.23 +/-0.10 3.18 +/-0.10 8.0 +/-0.3 1.55 +/-0.05 1.125 +/-0.125 1.75 +/-0.10 6.25 min 3.50 +/-0.05 4.0 +/-0.1 4.0 +/-0.1 1.37 +/-0.10 0.255 +/-0.150 5.2 +/-0.3 0.06 +/-0.02 supersot tm -6 tape and reel data, continued july 1999, rev. c
supersot ? -6 (fs pkg code 31, 33) supersot tm -6 package dimensions september 1998, rev. a 1:1 scale 1:1 on letter size paper dimensions shown below are in: inches [millimeters] part weight per unit (gram): 0.0158 ?2000 fairchild semiconductor international
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